The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus.
For very fast memory architectures with large scale integration, such as DDR-III DRAMs, “buffer chips” will be required in future. FIG. 1 illustrates such a memory system, in which the buffer chips 110, 210 situated on respective memory modules 100, 200 are connected in concatenated fashion to a primary memory bus 400 routed to a memory controller 300. On the buffer chips 110, 210, a switching arrangement S ensures that data are read from or written to the respective addressed memory module 100 or 200 only. The roman numerals I, II, III and IV denote individual memory groups with a respective plurality of memory chips situated in a row one behind the other on the memory modules 100 and 200. The buffer chips 110, 210 convert the “stub bus”, as used today in DDR and DDR-II systems, into a type of hierarchical bus system in which only point-to-point or point-to-two-point connections now arise. Such connections allow data transfer rates of far beyond one Gbps. In addition, cascading allows a large number of buffer chips to be concatenated with one another and allows memory systems having a very large number of memory chips to be produced on just one primary memory bus 400.
FIG. 2 illustrates a schematic layout view of how a memory module (DIMM) having a buffer chip 110 (HUB) and eight memory chips can be designed internally. Clock signal lines shown in dashes and dots and command and address bus lines (CIA) shown in dashes are driven centrally by the buffer chip 110, are routed in succession to the memory chips 101, 102, . . . 108 (DRAMs) in a “fly-by topology” and are terminated at the end by terminations a1, a2, b1, b2 in order to avoid signal reflections. The data bus lines (DQ), shown by solid lines in FIG. 2, in the DRAMs are connected to the buffer chip 110 separately as point-to-point connections.
At the high frequencies at which future computer systems and hence their memory systems will be operated, the propagation time of the signals on the aforementioned connecting lines is of fundamental importance. In the text below, 200 ps for each link (buffer chip to DRAM and DRAM to DRAM) will respectively be assumed for these propagation times. From the buffer chip 110 to the first DRAM (for example 104), all of the signals (CLK, C/A, DQ, DQS) thus require 200 ps, and 800 ps to the fourth DRAM (for example 101). Since the clock signal CLK and the command and address signal C/A have the same propagation time, commands and addresses can be transferred without difficulty from the buffer chip 110 to the respective DRAM chip. A similar situation applies for transferring write data (DQ, DQS) to the DRAMs. From the point of view of the overall system, the fact that the actual write operation in the DRAMs respectively takes place at different times is only of minor importance.
When data are to be read from the DRAMs, the following problem arises: the propagation times of the CLK signals and of the C/A signals on the bus mean that the DRAM chips receive the read command at different times. The difference between the first and the last DRAM in our example is 600 ps. After a certain time, which will be assumed to be the same for all DRAMs, the DRAM chips start to return their data to the buffer chip 110. The propagation time from the DRAM chip to the buffer chip is now again dependent on the position of the DRAM chip on the memory module (DIMM), with the propagation time in this arrangement being longest for the DRAM chip which received the command last. For this reason, the data will arrive at the buffer chip 110 with a time delay, specifically with a respective delay amounting to twice the propagation time from the buffer chip 110 to the DRAM chip. From the first to the last data, 1200 ps=1.2 ns therefore elapse.
This time delay in the read data either limits the maximum operating frequency to values which are significantly below 800 MHz (=1.125 ns) or needs to be compensated for by a complicated circuit in the buffer chip, which will result in a further delay in the data, since the earliest data can be forwarded with a delay of at least 1.2 ns plus the processing time in the compensation circuit.
DE 102 06 060 A1 describes a memory system in which each memory module has a plurality of memory chips and a buffer chip arranged on it. In read mode, the clock signals and the read signals have the same direction of propagation. This memory system has further basic differences as compared with the present semiconductor memory module: first, the data signals are supplied to the memory chips on the modules directly from a memory controller via spur lines. The propagation times of the command and address signals and of the data signals vary. Similarly, the respective propagation times of the read and write data signals from the respective memory modules to the memory controller are different. Finally, the known memory system has synchronous clock control for all of the memory modules as a result of the clock signal WCLK generated by the memory controller, and synchronous generation of the read clock signal RCLK in each buffer chip in each memory module.